Power Consumption on December 27, 2019 ASIC Backend design chip design Dynamic power leakage power Non Default Rules PD Physical Design Power Consumption power domain Semiconductor static power switching power VLSI +
Antenna Effect on December 25, 2019 Antenna Ratio ASIC PD Physical Design Physical Verification Semiconductor VLSI +
Crosstalk on November 15, 2019 Aggressor ASIC Backend design chip design clock tree synthesis Crosstalk NDR Analysis Non Default Rules PD Physical Design Semiconductor Victim VLSI +
Inverter Pair on November 11, 2019 ASIC Backend design Buffers CTS Inverter pair PD Physical Design Semiconductor VLSI +
Drive Strength on November 09, 2019 ASIC Buffers chip design Drive Drive Strength PD Physical Design Semiconductor +
DCD (Duty Cycle Distortion) on November 09, 2019 ASIC Backend design Buffers chip design clock buffers PD Physical Design Semiconductor Slew Transition time VLSI +
Impact of Clock Insertion Delay on different technology nodes on November 03, 2019 ASIC chip design Clock Tree clock tree synthesis CTS PD Physical Design VLSI +
NDR Analysis on November 01, 2019 ASIC Backend design chip design NDR Analysis Non Default Rules PD Physical Design VLSI +
Dummy LEF generation on November 01, 2019 ASIC Backend design chip design LEF PD Physical Design VLSI +