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on December 30, 2019

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AnonymousSeptember 24, 2020 at 6:26 AM
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Drive Strength

Drive strength of a cell is the measure of the ability to drive the load connected to it. More the drive strength more is the current carrying capability of the cell and more easy it is for the cell to sustain a larger load at output than one with a lower drive strength. Standard cells used in design may be according to different drive strengths of the cells available in the input library. For example AND1X, AND2X, AND3X, INV1X, INV2X, INV3X and so on are a few standard cells found in the library file. Likewise different filler cells or ECO cells may be classified based on different drive strengths. Now what does drive strength of a cell depend upon and how cells can be differentiated based on this. Well, drive strength depends on the ratio (w/l) of the transistor. Deciding on w/l ratio comes into sizing concepts for transistors. This can be manipulated during the standard cell design by increasing the number of fingers or the multiplication factor in the transistors. Smalle

Crosstalk

Now you might be wondering how we came down to the topic of crosstalk even with the presence of all the vast knowledge over the internet. But as I prefer to start on a simple issue and then extend into every possibility related to it this topic has been taken up. Crosstalk is defined as the undesirable electric interaction between two or more nets due to coupling capacitor between them. It occurs between parallel wires, usually due to the undesired capacitive, inductive or conductive coupling between the channels. It finally impacts the timing in the circuits. Crosstalk has two effects. 1. Crosstalk Delay- It implies the delay happening in the output transition of victim due to transition of aggressor. 2. Crosstalk Noise- This implies of the undesired changes in logical values of victim due to switching in the aggressor net. Fig1: Coupling between parallel nets When one net is switching and other net is at a constant value, the switching net may impact on the other net by

STA (Static Timing Analysis)

Static Timing Analysis is an approach to calculate the expected timing in a circuit from a small part of the design instead of going for the simulation of the full digital circuit to check the timing behavior of the same. In this process, specified values are used from additional look up tables to compute the timing behavior of the digital circuit. At this point the question that arises in our mind being, why an LUT in STA. Well the name itself mentions static that would mark its difference from its counterpart the Dynamic timing analysis method whereby a group of test vectors would be used to simulate the circuit in real time. Imagine the number of vectors that could be possible for 100 different paths and imagine the time that will be taken by a signoff tool to use these test sets in provided equations to come to the timing conclusions. It would definitely elongate the signoff time and would drastically delay the overall time in chip production causing a lag in technology advancemen

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