Buffers are cells used to condition a signal passing through them. They are used throughout the optimization process of PnR according to their availability in the supplied library design. Speaking of optimization, the buffers are used by the PnR tool to manage any violation that could occur in the data paths or clock paths of the design. As such, fixing of setup, hold, transition, fan-out and capacitance violations is possible using these buffers.
Impact of buffer introduction
Buffers are cells that divide a net to decrease the overall delay of the path/net according to the time constant relation given by:
T = RC where,
R = ρ.L/A
C = ε.A'/d
where T is the time constant, R the resistance of net and C the capacitance of the net and the rest are the constants and variables that aid the mathematical expressions for R and C. The simplified expression gives us T α L^2.
So if we use a buffer with a cell delay of 2 ps to break the net of 20ps delay into two parts. The proportionality expression changes to T' α (L/2)^2 with T' as the time taken by the divided branches. The fig 1 below shows the physical implication.
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| Fig 1: Net of 20 ps broken by buffer cell of 2 ps delay |
So each half of the net has now a reduced delay of 5ps each giving a total net delay of (5 + 2 + 5)ps ie, 12 ps. As such the reduction in delay due to use of a buffer is 8ps less than the net without a buffer.
Structure
The buffer cell actually has two inverters connected back to back with each other. One is the pre-driver which receives the signal and drives it to the inverter next to it while the second inverter(bigger in size than the first inverter) is the driver which decides the drive strength of the buffer. This is because the pre-driver cell sees the driver cell as the load which is much lower while on the other hand, the driver cell has larger size since has to supply the output load that is connected to the buffer output and it is much larger than the load for the first stage of the buffer cell. Fig2 shows the buffer structure (t1 < t2 and t3 < t2)
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| Fig2 Buffer structure |
- Regular Buffers are class of buffers that are used for conditioning data signals in the design. they have a smaller pre-driver size and as such the transition time t2 becomes larger to give a more diversion of t3 from t1. The regular buffers use lower metal layer for pins.
- Clock Buffers are another class of buffers that are used for conditioning the clock path and are used for optimization by the PnR tool during the clock tree synthesis stage. They are different from the regular buffers in the sense that they give almost equal rise and fall transition for a signal passing through them i.e, t1 and t3 in the fig2 are almost equal. This as such makes sure that there is lesser chance of any DCD (duty cycle distortion) in the clock tree. That's the sole reason that we can't use normal buffers in building a clock tree. Similar to the regular buffers, these clock buffers too have different drive strengths and different threshold voltages VT.
- They introduce better transition or slew to the signals through them
- As such leakage is pretty less
- Lower DCD issue than regular buffers
- They have lower threshold voltage as they have to deal with high frequency signal as clock
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