Power Consumption on December 27, 2019 ASIC Backend design chip design Dynamic power leakage power Non Default Rules PD Physical Design Power Consumption power domain Semiconductor static power switching power VLSI +
Crosstalk on November 15, 2019 Aggressor ASIC Backend design chip design clock tree synthesis Crosstalk NDR Analysis Non Default Rules PD Physical Design Semiconductor Victim VLSI +
Level Shifter on November 13, 2019 ASIC Backend design chip design cpf high voltage to low voltage low voltage Multi voltage Physical Design power domain Semiconductor upf VLSI +
Drive Strength on November 09, 2019 ASIC Buffers chip design Drive Drive Strength PD Physical Design Semiconductor +
DCD (Duty Cycle Distortion) on November 09, 2019 ASIC Backend design Buffers chip design clock buffers PD Physical Design Semiconductor Slew Transition time VLSI +
Buffers on November 09, 2019 ASIC Backend design Buffers chip design Physical Design Semiconductor Slew Transition time VLSI +
Transition Time of Signal on November 05, 2019 ASIC chip design Clock Tree Physical Design Slew Transition time VLSI +