Power Consumption on December 27, 2019 ASIC Backend design chip design Dynamic power leakage power Non Default Rules PD Physical Design Power Consumption power domain Semiconductor static power switching power VLSI +
Crosstalk on November 15, 2019 Aggressor ASIC Backend design chip design clock tree synthesis Crosstalk NDR Analysis Non Default Rules PD Physical Design Semiconductor Victim VLSI +
Level Shifter on November 13, 2019 ASIC Backend design chip design cpf high voltage to low voltage low voltage Multi voltage Physical Design power domain Semiconductor upf VLSI +
Inverter Pair on November 11, 2019 ASIC Backend design Buffers CTS Inverter pair PD Physical Design Semiconductor VLSI +
DCD (Duty Cycle Distortion) on November 09, 2019 ASIC Backend design Buffers chip design clock buffers PD Physical Design Semiconductor Slew Transition time VLSI +
Buffers on November 09, 2019 ASIC Backend design Buffers chip design Physical Design Semiconductor Slew Transition time VLSI +
NDR Analysis on November 01, 2019 ASIC Backend design chip design NDR Analysis Non Default Rules PD Physical Design VLSI +
Dummy LEF generation on November 01, 2019 ASIC Backend design chip design LEF PD Physical Design VLSI +