Antenna Effect

With shrinking technology effects of plasma during fabrication started showing negative pitfalls. A result of this is the Antenna Effect which is due to plasma induced gate breakdown. This can damage the transistor leading to yield and reliability problems during the process of IC manufacture.

During the manufacturing process a huge amount of charges are induced in plasma etching process. This happens due to the nature of plasma which consists of protons, neutrons and electrons with the electrons coming out loose from their atoms and molecules thereby giving the plasma the ability to act as a whole rather than a bunch of atoms. These electrons from plasma tend to accumulate near the channel region inducing opposite charges in the oxide edge of the gate. As a result an electric field gets generated whose strength depends on the induction process. These extra induced charge carriers might be too much for the gate to handle and the thin oxide layer is as such damaged. This is the reason Antenna ratio is more prominent in higher technology nodes as the shrinking technology causes shrinking in the oxide width too which cause more impact to damage. Fig1 shows the NMOS transistor where we can see the gate with the thin oxide layer that breaks down due to the electrons which get accumulated near the channel region during fabrication process

NMOS device

The gate terminal and the channel of a MOSFET will act as a capacitor with an oxide layer between the plate of the gate and the channel region in the substrate. Any net that need to undergo conditioning through a cell needs to be connected to the gate region of this transistor. This net will have a driver that will send the driven net to the cell under concern. Likewise, in this case the receiver is the gate terminal of the above device. The thin oxide layer will breakdown when the charges induced is more than its capacity and as such the electric field produced due to them becomes more causing the potential generated across the oxide layer to increase until the breakdown voltage is attained. This happens when metal layer connected to the gate is long and there is no path for its discharge when on this long layer higher layer gets stacked.Fig2 shows the transistor gate terminal acting as a capacitor plate.

fig2. Structure of oxide layer undergoing plasma induced charge accumulation

To give a measure of this mishap a parameter called Antenna Ratio is used. It is expressed as

A longer net(conductor) will have more area and the antenna ratio is higher. Because of this large length, the charge wouldn't be able to discharge and as such the build up will cause the gate to breakdown. As such higher the ratio AR, more are the probabilities of failure. 

The metal layers which are not connected to ground or other metal layers are called antenna. Hence, the name. The layers which are getting affected from this are the poly and metal layers.

Solving antenna violation

To fix antenna violation issues in our design our main aim should be to reduce the antenna ratio value. This can be done either by reducing the conductor area or increasing the total gate area. Gate area reduction is a manufacturing concern which is not in the hand of a design engineer. Leaky gate oxides are good for avoiding damage from antenna (bad power dissipation) but since I am talking from the design point of view let's discuss basically on fixing the conductor side.

• Firstly, considering the gate to be connected to diffusion through metal layer M1 which is a long wire, the conduction arc is more and this will as such contribute to antenna effect (the antenna ratio is higher than the minimum ratio).
  This can be solved by breaking the net near the gate which is possible by  the process of jumper insertion where the metal with violation is broken and connected to the next higher metal layer (in this case M2) through a via as shown in fig3 below. Jumpers are the metal connectors to switch to a higher parallel metal layer. During fabrication when metal 1 is being etched, metal 2 is not built yet and there is no diode connected to the gate oxide. The overall conduction area is as such reduced. However to hop into a higher layer one should be cautious that it should be done extremely near to the violating cell.

  

  fig3: using metal jumper to overcome antenna violation

   
• Next way is by adding a reverse biased diode to the conductor attached to the gate of the transistor. This step is undertaken if jogging into higher metal layer is not possible due to unavailability of routing tracks in the design near to the violating cell. Mostly n type diode is preferred over p type as the p type needs extra biasing of their Nwell. Now when the voltage on the node drops below substrate potential, this reverse biased diode gets forward biased and as such clamps the voltage thereby saving the gate of the transistor from breakdown. Fig4 gives the way in which diode insertion is done.

fig4: diode insertion for overcoming antenna violation

• Last resort for fixing antenna violation is using dummy devices in which the source and the drain are connected to ground while the gate is connected to the net. This will cause the charges to get distributed among the cells. This could be done when the net connected to the violating transistor is the highest routing layer and jogging is not an option. But it is hardly taken up.