Power Consumption

Power Consumption is an important criteria when continuity of current flow in an electrical circuit is concerned. Power is developed in any electrical circuit that has current and impedance quantities actively participating in it. Now this consumption may be either dynamic power consumption and static power consumption. Dynamic power consumption is named so because it occurs when the circuit is actively switching at the nodes. As such dynamic power is also called switching power. On the other hand, leakage in the system occurs when the circuit is not switching and so it is also called static power dissipation. With shrinking technology, deviation in behaviour for both the parameters are gradually changing and when technology started going below 90 nm, more significance came to be observed for the static power dissipation. While dynamic power dissipation prevailed of more importance in case of technology nodes greater than 90 nm.
In case of switching power the leakage current is due to the path created for current to flow as a result of the PMOS and the NMOS being on at the same time. As such the more is the slew of the signal at the input of a transistor the more is the leakage current that flows through. This is also called the crowbar current. The switching current can be represented by the expression

where, a is the switching activity, f is the frequency of operation, Ceff is the effective capacitance and Vdd is the supply voltage as we all understand.
As such the dynamic or switching power can be lowered by lowering the frequency, effective capacitance or the supply voltage.  Now for a particular technology, the lowering in the dynamic power can be done by the following ways

1. DVFS or Dynamic voltage and frequency scaling is a way to lower the dynamic power losses. In this process different voltage domains are introduced for modules operating at different frequencies. This is done in order to restrict the low frequency blocks from uselessly operating at higher voltages. However this is a complicated process which comes at the cost of more runtime for timing closure and also the usage of complex elements in the design. But the main aim of maintaining low power in the design and making the power supply to last longer is achieved. Hence DVFS is used. With the implementation of DVFS more corners and modes came into picture for timing closure which are the causes of increasing the runtime. 
2. Clock Gating is another way to reduce dynamic power consumption in which clock signal is allowed to pass through a smart logic inorder to restrict any production of glitch. Glitch is a component of noise and due to it's formation any control signal may be ruined leading to malfunctioning in the respective controlled block. An example could be made of a reset signal to a register which under the impact of glitch could reset the target register at the wrong time leading to a wrong data getting captured. Clock gating can also gate the clock from travelling to specific blocks in the design that need to be restricted from activity during any particular time. Fig1 shows a strategy of clock gating below.

Fig1: clock gating cell