STA (Static Timing Analysis)

Static Timing Analysis is an approach to calculate the expected timing in a circuit from a small part of the design instead of going for the simulation of the full digital circuit to check the timing behavior of the same. In this process, specified values are used from additional look up tables to compute the timing behavior of the digital circuit. At this point the question that arises in our mind being, why an LUT in STA. Well the name itself mentions static that would mark its difference from its counterpart the Dynamic timing analysis method whereby a group of test vectors would be used to simulate the circuit in real time. Imagine the number of vectors that could be possible for 100 different paths and imagine the time that will be taken by a signoff tool to use these test sets in provided equations to come to the timing conclusions. It would definitely elongate the signoff time and would drastically delay the overall time in chip production causing a lag in technology advancement.