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on December 29, 2019

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Drive Strength

Drive strength of a cell is the measure of the ability to drive the load connected to it. More the drive strength more is the current carrying capability of the cell and more easy it is for the cell to sustain a larger load at output than one with a lower drive strength. Standard cells used in design may be according to different drive strengths of the cells available in the input library. For example AND1X, AND2X, AND3X, INV1X, INV2X, INV3X and so on are a few standard cells found in the library file. Likewise different filler cells or ECO cells may be classified based on different drive strengths. Now what does drive strength of a cell depend upon and how cells can be differentiated based on this. Well, drive strength depends on the ratio (w/l) of the transistor. Deciding on w/l ratio comes into sizing concepts for transistors. This can be manipulated during the standard cell design by increasing the number of fingers or the multiplication factor in the transistors. Smalle

Level Shifter

Level shifter is a special cell in low power design that assists in the transition of signal flowing from one voltage domain to another voltage domain. Top level blocks in a chip may consist of multiple blocks inside it which have different functionality, and each of these blocks may have different power supplies too. This brings us to the concept of power domains in a design. In such a case, a signal in the chip passes from one power domain to another power domain. There may be as such twp different possibilities: Low voltage domain to high voltage domain. High voltage domain to low voltage domain. Now let's make an analysis if we really require a level shifter in the fist case i.e, Low voltage domain to high voltage domain Signal flowing from Low to high voltage domain Here in Fig 1 we can see the signal passing from 3.3V voltage domain to a 5V voltage domain. Fig2 CMOS Inverter Now in fig2 we have considered an inverter. Let us assume t

Crosstalk

Now you might be wondering how we came down to the topic of crosstalk even with the presence of all the vast knowledge over the internet. But as I prefer to start on a simple issue and then extend into every possibility related to it this topic has been taken up. Crosstalk is defined as the undesirable electric interaction between two or more nets due to coupling capacitor between them. It occurs between parallel wires, usually due to the undesired capacitive, inductive or conductive coupling between the channels. It finally impacts the timing in the circuits. Crosstalk has two effects. 1. Crosstalk Delay- It implies the delay happening in the output transition of victim due to transition of aggressor. 2. Crosstalk Noise- This implies of the undesired changes in logical values of victim due to switching in the aggressor net. Fig1: Coupling between parallel nets When one net is switching and other net is at a constant value, the switching net may impact on the other net by

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