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Drive Strength

Drive strength of a cell is the measure of the ability to drive the load connected to it. More the drive strength more is the current carrying capability of the cell and more easy it is for the cell to sustain a larger load at output than one with a lower drive strength. Standard cells used in design may be according to different drive strengths of the cells available in the input library. For example AND1X, AND2X, AND3X, INV1X, INV2X, INV3X and so on are a few standard cells found in the library file. Likewise different filler cells or ECO cells may be classified based on different drive strengths. Now what does drive strength of a cell depend upon and how cells can be differentiated based on this. Well, drive strength depends on the ratio (w/l) of the transistor. Deciding on w/l ratio comes into sizing concepts for transistors. This can be manipulated during the standard cell design by increasing the number of fingers or the multiplication factor in the transistors. Smalle...

Level Shifter

Level shifter is a special cell in low power design that assists in the transition of signal flowing from one voltage domain to another voltage domain. Top level blocks in a chip may consist of multiple blocks inside it which have different functionality, and each of these blocks may have different power supplies too. This brings us to the concept of power domains in a design. In such a case, a signal in the chip passes from one power domain to another power domain. There may be as such twp different possibilities: Low voltage domain to high voltage domain. High voltage domain to low voltage domain. Now let's make an analysis if we really require a level shifter in the fist case i.e, Low voltage domain to high voltage domain Signal flowing from Low to high voltage domain Here in Fig 1 we can see the signal passing from 3.3V voltage domain to a 5V voltage domain. Fig2 CMOS Inverter Now in fig2 we have considered an inverter. Let us assume t...

STA (Static Timing Analysis)

Static Timing Analysis is an approach to calculate the expected timing in a circuit from a small part of the design instead of going for the simulation of the full digital circuit to check the timing behavior of the same. In this process, specified values are used from additional look up tables to compute the timing behavior of the digital circuit. At this point the question that arises in our mind being, why an LUT in STA. Well the name itself mentions static that would mark its difference from its counterpart the Dynamic timing analysis method whereby a group of test vectors would be used to simulate the circuit in real time. Imagine the number of vectors that could be possible for 100 different paths and imagine the time that will be taken by a signoff tool to use these test sets in provided equations to come to the timing conclusions. It would definitely elongate the signoff time and would drastically delay the overall time in chip production causing a lag in technology advancemen...

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