Dummy LEF generation

LEF is the Library Exchange format of a design used in Cadence tools as input for PnR. LEF is in ASCII format. In case of Synopsys tools the same file is input as FRAM view which is a binary file. It basically consists the physical definition of the block or chip. These include the block dimensions, pin dimensions, pin directions, pin layers, symmetry of the design and the child blocks in the design, PG stripes' dimensions and placements, obstruction layer information and dimensions and placements of any other physical entity in the design.

Now coming to the topic under concern, I will start the insight with pipe-lining which implies that multiple tasks are performed in parallel in a mutually exclusive manner. Pipe-lining any group of tasks definitely saves time and optimizes output. Likewise in case of chip design, running different team tasks in parallel is the reason how technology gets updated within short spans otherwise we would have to live with the same cellular functions on our phone for generations. As a physical design engineer in order to overcome run cycle time of our design and obtain convergence in better scenarios, we can start the macro placement even before we get the actual LEF file of that block that needs to be implemented inside the design from the macro design team.

In this process, we create a dummy LEF file of that macro by taking the specifications like width, height, pin placement, timing constraints, IR drops, number of power stripes etc from the macro team and create a dummy LEF file using these information. This could be started by first creating a net-list with the parent block name as the name of the required macro and thereby instantiating an empty child block with the same inputs and outputs. The regular process of floor planning and pin placement and power ground planning is done on it using the PnR tool according to the given specifications which thereby dumps out the required LEF file with needed obstruction layers. Command for this in Innovus is:

>write_lef_abstract design_name.lef -stripePin
                                                           -PGPinLayers specified_pin_layer
                                                           -specifyTopLayer specified_top_layer
                                                           -version
This dummy macro design that we created can now act as a replacement till we get the actual macro. This way we don't even need to delay the run time of our block . It will save adequate design time and improve the cost metric which is always the main target of any design organization.