The amount of time taken by the clock signal to travel from source to the clock sink pin of the register is the clock insertion delay.
Clock insertion delay comprises of two components :
Clock insertion delay comprises of two components :
- clock source insertion delay
- clock network insertion delay
The amount of time taken by clock signal to travel from source (e.g PLL) to clock definition point is clock source insertion delay.
The amount of time taken by clock signal to travel from source to clock definition pin to clock sink pin of flip flop is clock network insertion delay.
Clock insertion delay denotes how big the clock tree is. If clock insertion delay is more it implies that the clock tree is large and hence higher is the uncertainty. On the other hand, if clock insertion delay is small it means the clock tree is small and hence smaller is the uncertainty. When the tool synthesizes the clock, the main aim is to minimize the skew and minimize the clock insertion delay. The insertion delay depends on the types of clock that feed the different components in different paths of the design. And these clock types depending on the distance of the clock sink from the source can be classified into
Clock insertion delay denotes how big the clock tree is. If clock insertion delay is more it implies that the clock tree is large and hence higher is the uncertainty. On the other hand, if clock insertion delay is small it means the clock tree is small and hence smaller is the uncertainty. When the tool synthesizes the clock, the main aim is to minimize the skew and minimize the clock insertion delay. The insertion delay depends on the types of clock that feed the different components in different paths of the design. And these clock types depending on the distance of the clock sink from the source can be classified into
- Raw clock (near to the PLL) with insertion delay less than 500 ps
- Small clock with insertion delay less than 1ns
- Medium clock with insertion delay somewhere around 1ns
- Large clock with insertion delay less than 2ns
- Very large clock with insertion delay less than 5ns
With growing reduction in technology nodes, the effect of clock insertion delay has become more prominent and as such more care has to be given to shortening the clock network to obtain optimized insertion delay.
The fig shows the classification of clocks based on the different insertion delay.
The fig shows the classification of clocks based on the different insertion delay.
- clk1 is a raw clock
- clk2 could be called a large clock that is far from the source and as such the clk2 insertion delay will be much more than clk1 insertion delay
- clk3 is a larger clock which would thereby have more insertion delay than then that of clk2
 |
| Fig specifying clock insertion delay |
How to minimize the clock insertion delay
By making the clock path as small as possible, we can optimize the clock tree from very large to large clock and as such we get uncertainty benefit which results in easier timing closure.
By making the clock path as small as possible, we can optimize the clock tree from very large to large clock and as such we get uncertainty benefit which results in easier timing closure.
Comments
Post a Comment