Power Consumption on December 27, 2019 ASIC Backend design chip design +9 Dynamic power leakage power Non Default Rules PD Physical Design Power Consumption power domain Semiconductor static power switching power VLSI ASIC Backend design chip design Dynamic power leakage power Non Default Rules PD Physical Design Power Consumption power domain Semiconductor static power switching power VLSI
Antenna Effect on December 25, 2019 Antenna Ratio ASIC PD Physical Design Physical Verification Semiconductor + VLSI Antenna Ratio ASIC PD Physical Design Physical Verification Semiconductor VLSI
Crosstalk on November 15, 2019 Aggressor ASIC Backend design +6 chip design clock tree synthesis Crosstalk NDR Analysis Non Default Rules PD Physical Design Semiconductor Victim VLSI Aggressor ASIC Backend design chip design clock tree synthesis Crosstalk NDR Analysis Non Default Rules PD Physical Design Semiconductor Victim VLSI
Level Shifter on November 13, 2019 ASIC Backend design chip design cpf +6 high voltage to low voltage low voltage Multi voltage Physical Design power domain Semiconductor upf VLSI ASIC Backend design chip design cpf high voltage to low voltage low voltage Multi voltage Physical Design power domain Semiconductor upf VLSI
Inverter Pair on November 11, 2019 ASIC Backend design Buffers CTS +2 Inverter pair PD Physical Design Semiconductor VLSI ASIC Backend design Buffers CTS Inverter pair PD Physical Design Semiconductor VLSI
Drive Strength on November 09, 2019 ASIC Buffers chip design Drive +1 Drive Strength PD Physical Design Semiconductor ASIC Buffers chip design Drive Drive Strength PD Physical Design Semiconductor